[xcc, sim] changed instruction format so imm12 subs for rs2

[riscv-isa-sim.git] / riscv / insns / div_s.h

diff --git a/riscv/insns/div_s.h b/riscv/insns/div_s.h
index b2d086910e1d4171ccd405b52465ee8c5583a0af..99e343c87dad6c758e165a5b8b7135e5e3f06d37 100644 (file)
--- a/riscv/insns/div_s.h
+++ b/riscv/insns/div_s.h
@@ -1,3 +1,3 @@
 require_fp;
-FRC = f32_div(FRA, FRB);
+FRDR = f32_div(FRS1, FRS2);
 set_fp_exceptions;