[xcc] minor performance tweaks

[riscv-isa-sim.git] / riscv / insns / divu.h

diff --git a/riscv/insns/divu.h b/riscv/insns/divu.h
index 9ccf01891c61094409658b9b231d83849a9e59a5..681afd217bbbda882d88de0c7a93848c8ed0d6fa 100644 (file)
--- a/riscv/insns/divu.h
+++ b/riscv/insns/divu.h
@@ -1,2 +1,4 @@
-RD = sext32(uint32_t(RS)/uint32_t(RT));
-
+if(RS2 == 0)
+  RD = UINT64_MAX;
+else
+  RD = sext_xprlen(zext_xprlen(RS1) / zext_xprlen(RS2));