[xcc] minor performance tweaks

[riscv-isa-sim.git] / riscv / insns / divuw.h

diff --git a/riscv/insns/divuw.h b/riscv/insns/divuw.h
index 296bb9e16f52d11fa5d13a4332792d2724ae851b..0ceb04025a017e6d8ea8ae723919d9f37cb3a6d0 100644 (file)
--- a/riscv/insns/divuw.h
+++ b/riscv/insns/divuw.h
@@ -1,4 +1,5 @@
-if(uint32_t(RS2) == 0)
-  RD = sext32(UINT32_MAX);
+require_xpr64;
+if(RS2 == 0)
+  RD = UINT64_MAX;
 else
-  RD = sext32(uint32_t(RS1)/uint32_t(RS2));
+  RD = sext32(zext32(RS1) / zext32(RS2));