[xcc] minor performance tweaks

[riscv-isa-sim.git] / riscv / insns / divuw.h

diff --git a/riscv/insns/divuw.h b/riscv/insns/divuw.h
index f52fe5a536834ef372ef8c7e8bb1526ca6678629..0ceb04025a017e6d8ea8ae723919d9f37cb3a6d0 100644 (file)
--- a/riscv/insns/divuw.h
+++ b/riscv/insns/divuw.h
@@ -1,2 +1,5 @@
-RDR = sext32(uint32_t(RS1)/uint32_t(RS2));
-
+require_xpr64;
+if(RS2 == 0)
+  RD = UINT64_MAX;
+else
+  RD = sext32(zext32(RS1) / zext32(RS2));