Use WRITE_RD/WRITE_FRD macros to write registers

[riscv-isa-sim.git] / riscv / insns / divuw.h

diff --git a/riscv/insns/divuw.h b/riscv/insns/divuw.h
index 7f6e32115c9d7bcd7ef1b98b93cdbbed302406e0..a7176580ba5c90909f812bd15cbd5735a23f081e 100644 (file)
--- a/riscv/insns/divuw.h
+++ b/riscv/insns/divuw.h
@@ -2,6 +2,6 @@ require_xpr64;
 reg_t lhs = zext32(RS1);
 reg_t rhs = zext32(RS2);
 if(rhs == 0)
-  RD = UINT64_MAX;
+  WRITE_RD(UINT64_MAX);
 else
-  RD = sext32(lhs / rhs);
+  WRITE_RD(sext32(lhs / rhs));