[xcc, sim] changed instruction format so imm12 subs for rs2

[riscv-isa-sim.git] / riscv / insns / divw.h

diff --git a/riscv/insns/divw.h b/riscv/insns/divw.h
index e595c85af0c8af441552ac7fa3a7c9d84d4721a8..938478c0c9391da50e27e84486804b1839a20c12 100644 (file)
--- a/riscv/insns/divw.h
+++ b/riscv/insns/divw.h
@@ -1,2 +1,2 @@
-RC = sext32(int32_t(RA)/int32_t(RB));
+RDR = sext32(int32_t(RS1)/int32_t(RS2));