[sim] fixed some compiler warnings

[riscv-isa-sim.git] / riscv / insns / divw.h

diff --git a/riscv/insns/divw.h b/riscv/insns/divw.h
index 05374695b7c3016c783f836cbe60673bd70d7c89..bfc982a7a50329ad7eab76a3395cc8a34f94eb0f 100644 (file)
--- a/riscv/insns/divw.h
+++ b/riscv/insns/divw.h
@@ -1,4 +1,4 @@
-if(int32_t(RS2) == 0 || int32_t(RS1) == INT32_MIN && int32_t(RS2) == -1)
+if(int32_t(RS2) == 0 || (int32_t(RS1) == INT32_MIN && int32_t(RS2) == -1))
   RD = sext32(int32_t(RS1) < 0 ? INT32_MIN : INT32_MAX);
 else
   RD = sext32(int32_t(RS1)/int32_t(RS2));