new supervisor mode

[riscv-isa-sim.git] / riscv / insns / eret.h

diff --git a/riscv/insns/eret.h b/riscv/insns/eret.h
index 46d5bed27ef40a8f8af61607c67933ff30b73c46..cd968bdeb41c4b60d947880d8aedbb7066d5e2e0 100644 (file)
--- a/riscv/insns/eret.h
+++ b/riscv/insns/eret.h
@@ -1,5 +1,5 @@
 require_supervisor;
 if(sr & SR_ET)
   throw trap_illegal_instruction;
-set_sr(((sr & SR_PS) ? sr : (sr & ~SR_S)) | SR_ET);
+set_pcr(PCR_SR, ((sr & SR_PS) ? sr : (sr & ~SR_S)) | SR_ET);
 set_pc(epc);