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Use WRITE_RD/WRITE_FRD macros to write registers
[riscv-isa-sim.git]
/
riscv
/
insns
/
fdiv_d.h
diff --git
a/riscv/insns/fdiv_d.h
b/riscv/insns/fdiv_d.h
index aa00c98dcae8ae2e77c30f0e3ed933fa52619c1e..e21570278522f29d4cdc21afd403c3e2baea8377 100644
(file)
--- a/
riscv/insns/fdiv_d.h
+++ b/
riscv/insns/fdiv_d.h
@@
-1,4
+1,4
@@
require_fp;
softfloat_roundingMode = RM;
-
FRD = f64_div(FRS1, FRS2
);
+
WRITE_FRD(f64_div(FRS1, FRS2)
);
set_fp_exceptions;