Use WRITE_RD/WRITE_FRD macros to write registers

[riscv-isa-sim.git] / riscv / insns / feq_d.h

diff --git a/riscv/insns/feq_d.h b/riscv/insns/feq_d.h
index 9db876060e2d2cab82419356644baea24e26165f..516fb5965cb1dac9525b17428fe73770c1015581 100644 (file)
--- a/riscv/insns/feq_d.h
+++ b/riscv/insns/feq_d.h
@@ -1,3 +1,3 @@
 require_fp;
-RD = f64_eq(FRS1, FRS2);
+WRITE_RD(f64_eq(FRS1, FRS2));
 set_fp_exceptions;