Upgrade to latest SoftFloat
[riscv-isa-sim.git] / riscv / insns / feq_s.h
index 7d426345aaf04b65ce18faf106122f00f350bc6c..489bea693836c445c47307049d920645be72635d 100644 (file)
@@ -1,4 +1,4 @@
 require_extension('F');
 require_fp;
-WRITE_RD(f32_eq(FRS1, FRS2));
+WRITE_RD(f32_eq(f32(FRS1), f32(FRS2)));
 set_fp_exceptions;