Use WRITE_RD/WRITE_FRD macros to write registers

[riscv-isa-sim.git] / riscv / insns / fle_d.h

diff --git a/riscv/insns/fle_d.h b/riscv/insns/fle_d.h
index da7618725c8c6cfd1d18f7d5b44fe3699b717eba..72dcc7e650560d450c357cb43b83e6d373ab64d5 100644 (file)
--- a/riscv/insns/fle_d.h
+++ b/riscv/insns/fle_d.h
@@ -1,3 +1,3 @@
 require_fp;
-RD = f64_le(FRS1, FRS2);
+WRITE_RD(f64_le(FRS1, FRS2));
 set_fp_exceptions;