Use WRITE_RD/WRITE_FRD macros to write registers

[riscv-isa-sim.git] / riscv / insns / fle_s.h

diff --git a/riscv/insns/fle_s.h b/riscv/insns/fle_s.h
index 9c83a17f00135d71f5d6a2fa23bafe4732af74a5..9c85b4a586b750fc74657dd652555300a7e9c227 100644 (file)
--- a/riscv/insns/fle_s.h
+++ b/riscv/insns/fle_s.h
@@ -1,3 +1,3 @@
 require_fp;
-RD = f32_le(FRS1, FRS2);
+WRITE_RD(f32_le(FRS1, FRS2));
 set_fp_exceptions;