Use WRITE_RD/WRITE_FRD macros to write registers

[riscv-isa-sim.git] / riscv / insns / flt_d.h

diff --git a/riscv/insns/flt_d.h b/riscv/insns/flt_d.h
index 01d135a93de845723f52517502feea8c98613aba..335e4a80125d47d0d1e0ead1097c0c3123cbeb4f 100644 (file)
--- a/riscv/insns/flt_d.h
+++ b/riscv/insns/flt_d.h
@@ -1,3 +1,3 @@
 require_fp;
-RD = f64_lt(FRS1, FRS2);
+WRITE_RD(f64_lt(FRS1, FRS2));
 set_fp_exceptions;