Fix implementation of FMIN/FMAX NaN case

[riscv-isa-sim.git] / riscv / insns / fmin_s.h

diff --git a/riscv/insns/fmin_s.h b/riscv/insns/fmin_s.h
index 80990035a6004a721261d57eabda019589fc95d2..19e119381df1c2ae64d2e9d26c799080b8c580e0 100644 (file)
--- a/riscv/insns/fmin_s.h
+++ b/riscv/insns/fmin_s.h
@@ -2,7 +2,8 @@ require_extension('F');
 require_fp;
 bool less = f32_lt_quiet(f32(FRS1), f32(FRS2)) ||
             (f32_eq(f32(FRS1), f32(FRS2)) && (f32(FRS1).v & F32_SIGN));
-WRITE_FRD(less || isNaNF32UI(f32(FRS2).v) ? FRS1 : FRS2);
 if (isNaNF32UI(f32(FRS1).v) && isNaNF32UI(f32(FRS2).v))
   WRITE_FRD(f32(defaultNaNF32UI));
+else
+  WRITE_FRD(less || isNaNF32UI(f32(FRS2).v) ? FRS1 : FRS2);
 set_fp_exceptions;