Upgrade to latest SoftFloat
[riscv-isa-sim.git] / riscv / insns / fmsub_s.h
index 92512772c6d4c0ada2fe52133024847207b927cd..45945dac4a48fd1230ddc5174e94a9915c896a24 100644 (file)
@@ -1,5 +1,5 @@
 require_extension('F');
 require_fp;
 softfloat_roundingMode = RM;
-WRITE_FRD(f32_mulAdd(FRS1, FRS2, FRS3 ^ (uint32_t)INT32_MIN));
+WRITE_FRD(f32_mulAdd(f32(FRS1), f32(FRS2), f32(FRS3 ^ (uint32_t)INT32_MIN)).v);
 set_fp_exceptions;