Use WRITE_RD/WRITE_FRD macros to write registers

[riscv-isa-sim.git] / riscv / insns / jalr.h

diff --git a/riscv/insns/jalr.h b/riscv/insns/jalr.h
index fa6d7f1fdb04b4e70307c309f4ab7a46022c9853..3924aa45f3cf54536d6c292acd1cec22a950eb3d 100644 (file)
--- a/riscv/insns/jalr.h
+++ b/riscv/insns/jalr.h
@@ -1,3 +1,3 @@
 reg_t temp = RS1;
-RD = npc;
+WRITE_RD(npc);
 set_pc((temp + insn.i_imm()) & ~1);