Use WRITE_RD/WRITE_FRD macros to write registers

[riscv-isa-sim.git] / riscv / insns / lb.h

diff --git a/riscv/insns/lb.h b/riscv/insns/lb.h
index 36acd7bd719063ccf3012ea48ed5efe02e5205fa..0f0999caa385317e543baca04266e73d63febe7f 100644 (file)
--- a/riscv/insns/lb.h
+++ b/riscv/insns/lb.h
@@ -1 +1 @@
-RD = MMU.load_int8(RS1 + insn.i_imm());
+WRITE_RD(MMU.load_int8(RS1 + insn.i_imm()));