[xcc] minor performance tweaks

[riscv-isa-sim.git] / riscv / insns / lb.h

diff --git a/riscv/insns/lb.h b/riscv/insns/lb.h
index ac8bf6486307d693e5d7d156a52cbeabdb29a2c9..81ba7dec7f4c28c95007b651ca88e08babeb365a 100644 (file)
--- a/riscv/insns/lb.h
+++ b/riscv/insns/lb.h
@@ -1 +1 @@
-RA = mmu.load_int8(RB+SIMM);
+RD = mmu.load_int8(RS1+SIMM);