[xcc] minor performance tweaks

[riscv-isa-sim.git] / riscv / insns / lbu.h

diff --git a/riscv/insns/lbu.h b/riscv/insns/lbu.h
index 522eb8f98c16c92bffe61a6e314941b589aeb587..12c688a2ce566352d557f858804b83f4aedd43dd 100644 (file)
--- a/riscv/insns/lbu.h
+++ b/riscv/insns/lbu.h
@@ -1 +1 @@
-RA = mmu.load_uint8(RB+SIMM);
+RD = mmu.load_uint8(RS1+SIMM);