[xcc, sim] changed instruction format so imm12 subs for rs2

[riscv-isa-sim.git] / riscv / insns / lbu.h

diff --git a/riscv/insns/lbu.h b/riscv/insns/lbu.h
index 522eb8f98c16c92bffe61a6e314941b589aeb587..e378871edc14052d4b118a4663f6c56d0ccc35f9 100644 (file)
--- a/riscv/insns/lbu.h
+++ b/riscv/insns/lbu.h
@@ -1 +1 @@
-RA = mmu.load_uint8(RB+SIMM);
+RDI = mmu.load_uint8(RS1+SIMM);