[xcc, sim] changed instruction format so imm12 subs for rs2

[riscv-isa-sim.git] / riscv / insns / ld.h

diff --git a/riscv/insns/ld.h b/riscv/insns/ld.h
index 241af6a1acb19e48bd93bad03d1b3ab5ef847be5..9959d2698d828c46726dd892e8ccec6e32cd3357 100644 (file)
--- a/riscv/insns/ld.h
+++ b/riscv/insns/ld.h
@@ -1,2 +1,2 @@
 require64;
-RA = mmu.load_int64(RB+SIMM);
+RDI = mmu.load_int64(RS1+SIMM);