[xcc] minor performance tweaks

[riscv-isa-sim.git] / riscv / insns / lhu.h

diff --git a/riscv/insns/lhu.h b/riscv/insns/lhu.h
index 6d77f0489201c50522114f762bb532a8514bfb4a..0999c0017b75d3df274758911b30326b8ff60f03 100644 (file)
--- a/riscv/insns/lhu.h
+++ b/riscv/insns/lhu.h
@@ -1 +1 @@
-RT = mmu.load_uint16(RS+SIMM);
+RD = mmu.load_uint16(RS1+SIMM);