[xcc, sim] changed instruction format so imm12 subs for rs2

[riscv-isa-sim.git] / riscv / insns / lui.h

diff --git a/riscv/insns/lui.h b/riscv/insns/lui.h
index 0eb14bc4010af13a49d0226cc587bf675a233d0b..20a0af841fed2321730dda69b0e2ab98b4fca050 100644 (file)
--- a/riscv/insns/lui.h
+++ b/riscv/insns/lui.h
@@ -1 +1 @@
-RA = sext32(BIGIMM << IMM_BITS);
+RDI = sext32(BIGIMM << IMM_BITS);