[xcc] minor performance tweaks

[riscv-isa-sim.git] / riscv / insns / lw.h

diff --git a/riscv/insns/lw.h b/riscv/insns/lw.h
index 6bd26463adba7445d6b2cc1569bbc4b9f4520edd..769c9fd9306c324eee0e2959b788423def816569 100644 (file)
--- a/riscv/insns/lw.h
+++ b/riscv/insns/lw.h
@@ -1 +1 @@
-RDI = mmu.load_int32(RS1+SIMM);
+RD = mmu.load_int32(RS1+SIMM);