[xcc, sim] changed instruction format so imm12 subs for rs2

[riscv-isa-sim.git] / riscv / insns / lwu.h

diff --git a/riscv/insns/lwu.h b/riscv/insns/lwu.h
index 311292d8022ad8d29d80d2d902a216fbc1384e66..3c597af1da84af4b0bd5ca39f46c25795392d211 100644 (file)
--- a/riscv/insns/lwu.h
+++ b/riscv/insns/lwu.h
@@ -1 +1 @@
-RA = mmu.load_uint32(RB+SIMM);
+RDI = mmu.load_uint32(RS1+SIMM);