[xcc] minor performance tweaks

[riscv-isa-sim.git] / riscv / insns / lwu.h

diff --git a/riscv/insns/lwu.h b/riscv/insns/lwu.h
index 5e62b0f09b5449c154f0797f8bef01557b687cf8..f8f98414f58aa6132f61ea32202fce8176a28994 100644 (file)
--- a/riscv/insns/lwu.h
+++ b/riscv/insns/lwu.h
@@ -1 +1,2 @@
+require_xpr64;
 RD = mmu.load_uint32(RS1+SIMM);