[xcc, sim] changed instruction format so imm12 subs for rs2

[riscv-isa-sim.git] / riscv / insns / mfcr.h

diff --git a/riscv/insns/mfcr.h b/riscv/insns/mfcr.h
index 088480cba7e4f18c96b5998a98284084df67cf25..1d6b4d153857d665c3a74983a5baae9dab6d5ea1 100644 (file)
--- a/riscv/insns/mfcr.h
+++ b/riscv/insns/mfcr.h
@@ -1,6 +1,6 @@
 reg_t val;
 
-switch(insn.rtype.rb)
+switch(insn.rtype.rs2)
 {
   case 0:
     val = fsr;
@@ -18,4 +18,4 @@ switch(insn.rtype.rb)
     val = -1;
 }
 
-RC = gprlen == 64 ? val : sext32(val);
+RDR = gprlen == 64 ? val : sext32(val);