[xcc, sim] changed instruction format so imm12 subs for rs2

[riscv-isa-sim.git] / riscv / insns / mff_d.h

diff --git a/riscv/insns/mff_d.h b/riscv/insns/mff_d.h
index e2e8415ce81e2a5a47cf5b4a214a88ec8d63466b..1f0182eb26365aea4170bfc152a16acbc52abd98 100644 (file)
--- a/riscv/insns/mff_d.h
+++ b/riscv/insns/mff_d.h
@@ -1,3 +1,3 @@
 require64;
 require_fp;
-RC = FRA;
+RDR = FRS1;