[xcc, sim] changed instruction format so imm12 subs for rs2

[riscv-isa-sim.git] / riscv / insns / mff_s.h

diff --git a/riscv/insns/mff_s.h b/riscv/insns/mff_s.h
index f92c935266ad9f55bb92b2003ea0800635242750..a258aa088ab3e58dacbdbab6fc3ac8df289fe6a7 100644 (file)
--- a/riscv/insns/mff_s.h
+++ b/riscv/insns/mff_s.h
@@ -1,2 +1,2 @@
 require_fp;
-RC = sext32(FRA);
+RDR = sext32(FRS1);