[xcc] minor performance tweaks

[riscv-isa-sim.git] / riscv / insns / mfpcr.h

diff --git a/riscv/insns/mfpcr.h b/riscv/insns/mfpcr.h
index 54c62edccfe80b0d496c696384233fdea20f4532..e0c67ae1fd42708d47f8b72b31a7d173a05a4fd5 100644 (file)
--- a/riscv/insns/mfpcr.h
+++ b/riscv/insns/mfpcr.h
@@ -25,9 +25,29 @@ switch(insn.rtype.rs2)
   case 6:
     val = cause;
     break;
+  case 7:
+    val = 0;
+    cause &= ~(1 << (IPI_IRQ+CAUSE_IP_SHIFT));
+    break;
 
   case 8:
-    val = MEMSIZE >> 12;
+    val = mmu.memsz >> PGSHIFT;
+    break;
+
+  case 9:
+    val = mmu.get_ptbr();
+    break;
+
+  case 10:
+    val = id;
+    break;
+
+  case 11:
+    val = vecbanks;
+    break;
+
+  case 12:
+    val = sim->num_cores();
     break;
 
   case 17:
@@ -45,4 +65,4 @@ switch(insn.rtype.rs2)
     val = -1;
 }
 
-RD = gprlen == 64 ? val : sext32(val);
+RD = sext_xprlen(val);