[xcc] minor performance tweaks

[riscv-isa-sim.git] / riscv / insns / mfpcr.h

diff --git a/riscv/insns/mfpcr.h b/riscv/insns/mfpcr.h
index 7808458722cb48d4573bab9f979c12313f7c7e29..e0c67ae1fd42708d47f8b72b31a7d173a05a4fd5 100644 (file)
--- a/riscv/insns/mfpcr.h
+++ b/riscv/insns/mfpcr.h
@@ -1,29 +1,68 @@
 require_supervisor;
-require64;
 
-switch(insn.rtype.rb)
+reg_t val;
+
+switch(insn.rtype.rs2)
 {
   case 0:
-    RA = sr;
+    val = sr;
     break;
   case 1:
-    RA = epc;
+    val = epc;
     break;
   case 2:
-    RA = badvaddr;
+    val = badvaddr;
     break;
   case 3:
-    RA = ebase;
+    val = evec;
+    break;
+  case 4:
+    val = count;
+    break;
+  case 5:
+    val = compare;
+    break;
+  case 6:
+    val = cause;
+    break;
+  case 7:
+    val = 0;
+    cause &= ~(1 << (IPI_IRQ+CAUSE_IP_SHIFT));
     break;
 
   case 8:
-    RA = MEMSIZE >> 12;
+    val = mmu.memsz >> PGSHIFT;
+    break;
+
+  case 9:
+    val = mmu.get_ptbr();
+    break;
+
+  case 10:
+    val = id;
+    break;
+
+  case 11:
+    val = vecbanks;
+    break;
+
+  case 12:
+    val = sim->num_cores();
     break;
 
   case 17:
-    RA = sim->get_fromhost();
+    fromhost = val = sim->get_fromhost();
+    break;
+
+  case 24:
+    val = pcr_k0;
+    break;
+  case 25:
+    val = pcr_k1;
     break;
 
   default:
-    RA = -1;
+    val = -1;
 }
+
+RD = sext_xprlen(val);