[xcc] minor performance tweaks

[riscv-isa-sim.git] / riscv / insns / mfpcr.h

diff --git a/riscv/insns/mfpcr.h b/riscv/insns/mfpcr.h
index b151150f421c5ce05109a29f807ae606ff0d9abd..e0c67ae1fd42708d47f8b72b31a7d173a05a4fd5 100644 (file)
--- a/riscv/insns/mfpcr.h
+++ b/riscv/insns/mfpcr.h
@@ -26,11 +26,12 @@ switch(insn.rtype.rs2)
     val = cause;
     break;
   case 7:
+    val = 0;
     cause &= ~(1 << (IPI_IRQ+CAUSE_IP_SHIFT));
     break;
 
   case 8:
-    val = MEMSIZE >> PGSHIFT;
+    val = mmu.memsz >> PGSHIFT;
     break;
 
   case 9: