[xcc] minor performance tweaks

[riscv-isa-sim.git] / riscv / insns / mfpcr.h

diff --git a/riscv/insns/mfpcr.h b/riscv/insns/mfpcr.h
index b72b850416fb3b115917bba3dd071276315c974f..e0c67ae1fd42708d47f8b72b31a7d173a05a4fd5 100644 (file)
--- a/riscv/insns/mfpcr.h
+++ b/riscv/insns/mfpcr.h
@@ -25,9 +25,13 @@ switch(insn.rtype.rs2)
   case 6:
     val = cause;
     break;
+  case 7:
+    val = 0;
+    cause &= ~(1 << (IPI_IRQ+CAUSE_IP_SHIFT));
+    break;
 
   case 8:
-    val = MEMSIZE >> PGSHIFT;
+    val = mmu.memsz >> PGSHIFT;
     break;
 
   case 9: