[xcc] minor performance tweaks

[riscv-isa-sim.git] / riscv / insns / mfpcr.h

diff --git a/riscv/insns/mfpcr.h b/riscv/insns/mfpcr.h
index d9bfc223f20d1a0de02c02d3ac7b559dde8f94d8..e0c67ae1fd42708d47f8b72b31a7d173a05a4fd5 100644 (file)
--- a/riscv/insns/mfpcr.h
+++ b/riscv/insns/mfpcr.h
@@ -2,7 +2,7 @@ require_supervisor;
 
 reg_t val;
 
-switch(insn.rtype.rb)
+switch(insn.rtype.rs2)
 {
   case 0:
     val = sr;
@@ -14,15 +14,44 @@ switch(insn.rtype.rb)
     val = badvaddr;
     break;
   case 3:
-    val = ebase;
+    val = evec;
+    break;
+  case 4:
+    val = count;
+    break;
+  case 5:
+    val = compare;
+    break;
+  case 6:
+    val = cause;
+    break;
+  case 7:
+    val = 0;
+    cause &= ~(1 << (IPI_IRQ+CAUSE_IP_SHIFT));
     break;
 
   case 8:
-    val = MEMSIZE >> 12;
+    val = mmu.memsz >> PGSHIFT;
+    break;
+
+  case 9:
+    val = mmu.get_ptbr();
+    break;
+
+  case 10:
+    val = id;
+    break;
+
+  case 11:
+    val = vecbanks;
+    break;
+
+  case 12:
+    val = sim->num_cores();
     break;
 
   case 17:
-    val = sim->get_fromhost();
+    fromhost = val = sim->get_fromhost();
     break;
 
   case 24:
@@ -36,4 +65,4 @@ switch(insn.rtype.rb)
     val = -1;
 }
 
-RC = gprlen == 64 ? val : sext32(val);
+RD = sext_xprlen(val);