[xcc, sim] changed instruction format so imm12 subs for rs2

[riscv-isa-sim.git] / riscv / insns / mtf_d.h

diff --git a/riscv/insns/mtf_d.h b/riscv/insns/mtf_d.h
index 4d3983335fe49dd835fef9e97a797a4cb52ddc09..6777689b948ff6f593df9d512a479cc6d1425bbc 100644 (file)
--- a/riscv/insns/mtf_d.h
+++ b/riscv/insns/mtf_d.h
@@ -1,3 +1,3 @@
 require64;
 require_fp;
-FRC = RA;
+FRDR = RS1;