[xcc, sim] changed instruction format so imm12 subs for rs2

[riscv-isa-sim.git] / riscv / insns / mtf_s.h

diff --git a/riscv/insns/mtf_s.h b/riscv/insns/mtf_s.h
index 723a2f704d6a05e77cfd100b7ce17e17405f8737..a1c22fddce956f5606c6f9842358fa6cbda694e2 100644 (file)
--- a/riscv/insns/mtf_s.h
+++ b/riscv/insns/mtf_s.h
@@ -1,2 +1,2 @@
 require_fp;
-FRC = RA;
+FRDR = RS1;