[xcc, sim] changed instruction format so imm12 subs for rs2

[riscv-isa-sim.git] / riscv / insns / mtflh_d.h

diff --git a/riscv/insns/mtflh_d.h b/riscv/insns/mtflh_d.h
index 4e33f399bdefa85ac4c1dc3dfedf13021c30d824..c48c726314bc7ddc92949916707cdfdf67617402 100644 (file)
--- a/riscv/insns/mtflh_d.h
+++ b/riscv/insns/mtflh_d.h
@@ -1,2 +1,2 @@
 require_fp;
-FRC = (RA & 0x00000000FFFFFFFF) | (RB << 32);
+FRDR = (RS1 & 0x00000000FFFFFFFF) | (RS2 << 32);