[xcc] minor performance tweaks

[riscv-isa-sim.git] / riscv / insns / mtpcr.h

diff --git a/riscv/insns/mtpcr.h b/riscv/insns/mtpcr.h
index bcc613a52f27264f4ce7323252789ad71edd27d0..46fbfdb23375ecd01955678a68a18adf178d6722 100644 (file)
--- a/riscv/insns/mtpcr.h
+++ b/riscv/insns/mtpcr.h
@@ -9,16 +9,29 @@ switch(insn.rtype.rs2)
     epc = RS1;
     break;
   case 3:
-    ebase = RS1 & ~0xFFF;
+    evec = RS1;
     break;
   case 4:
     count = RS1;
     break;
   case 5:
-    interrupts_pending &= ~(1 << TIMER_IRQ);
+    cause &= ~(1 << (TIMER_IRQ+CAUSE_IP_SHIFT));
     compare = RS1;
     break;
 
+  case 7:
+    sim->send_ipi(RS1);
+    break;
+
+  case 9:
+    mmu.set_ptbr(RS1);
+    break;
+
+  case 11:
+    vecbanks = RS1 & 0xff;
+    vecbanks_count = __builtin_popcountll(vecbanks);
+    break;
+
   case 16:
     tohost = RS1;
     sim->set_tohost(RS1);