[xcc] minor performance tweaks

[riscv-isa-sim.git] / riscv / insns / mtpcr.h

diff --git a/riscv/insns/mtpcr.h b/riscv/insns/mtpcr.h
index cbb580b52d152bc969aa299eeb9aca46f531680b..46fbfdb23375ecd01955678a68a18adf178d6722 100644 (file)
--- a/riscv/insns/mtpcr.h
+++ b/riscv/insns/mtpcr.h
@@ -1,27 +1,46 @@
 require_supervisor;
 
-reg_t val = gprlen == 64 ? RA : sext32(RA);
-
-switch(insn.rtype.rb)
+switch(insn.rtype.rs2)
 {
   case 0:
-    set_sr(val);
+    set_sr(RS1);
     break;
   case 1:
-    epc = val;
+    epc = RS1;
     break;
   case 3:
-    ebase = val & ~0xFFF;
+    evec = RS1;
+    break;
+  case 4:
+    count = RS1;
+    break;
+  case 5:
+    cause &= ~(1 << (TIMER_IRQ+CAUSE_IP_SHIFT));
+    compare = RS1;
+    break;
+
+  case 7:
+    sim->send_ipi(RS1);
+    break;
+
+  case 9:
+    mmu.set_ptbr(RS1);
+    break;
+
+  case 11:
+    vecbanks = RS1 & 0xff;
+    vecbanks_count = __builtin_popcountll(vecbanks);
     break;
 
   case 16:
-    sim->set_tohost(val);
+    tohost = RS1;
+    sim->set_tohost(RS1);
     break;
 
   case 24:
-    pcr_k0 = val;
+    pcr_k0 = RS1;
     break;
   case 25:
-    pcr_k1 = val;
+    pcr_k1 = RS1;
     break;
 }