new supervisor mode

[riscv-isa-sim.git] / riscv / insns / mtpcr.h

diff --git a/riscv/insns/mtpcr.h b/riscv/insns/mtpcr.h
index f06fcf30ebcf117b561a0da5c1d57c06f9f474eb..5cd0134e0ba933c08df7daebe9b953354508b747 100644 (file)
--- a/riscv/insns/mtpcr.h
+++ b/riscv/insns/mtpcr.h
@@ -1,47 +1,4 @@
 require_supervisor;
-
-switch(insn.rtype.rs2)
-{
-  case 0:
-    set_sr(RS1);
-    break;
-  case 1:
-    epc = RS1;
-    break;
-  case 3:
-    evec = RS1;
-    break;
-  case 4:
-    count = RS1;
-    break;
-  case 5:
-    interrupts_pending &= ~(1 << TIMER_IRQ);
-    compare = RS1;
-    break;
-  case 7:
-    mmu.set_ptbr(RS1);
-    break;
-
-  case 8:
-    sim.send_ipi(RS1);
-    break;
-  case 9:
-    interrupts_pending &= ~(1 << IPI_IRQ);
-    break;
-
-  case 12:
-    pcr_k0 = RS1;
-    break;
-  case 13:
-    pcr_k1 = RS1;
-    break;
-
-  case 16:
-    sim.set_tohost(RS1);
-    break;
-
-  case 18:
-    vecbanks = RS1 & 0xff;
-    vecbanks_count = __builtin_popcountll(vecbanks);
-    break;
-}
+reg_t val = get_pcr(insn.rtype.rs1);
+set_pcr(insn.rtype.rs1, RS2);
+RD = val;