[xcc, sim] changed instruction format so imm12 subs for rs2

[riscv-isa-sim.git] / riscv / insns / mul_s.h

diff --git a/riscv/insns/mul_s.h b/riscv/insns/mul_s.h
index d700d846fa3d23a2533eeedbf1bc55daf82d7077..5c1397c5a1c4f9a65623fb377da6c4318f72edbb 100644 (file)
--- a/riscv/insns/mul_s.h
+++ b/riscv/insns/mul_s.h
@@ -1,3 +1,3 @@
 require_fp;
-FRC = f32_mul(FRA, FRB);
+FRDR = f32_mul(FRS1, FRS2);
 set_fp_exceptions;