[xcc, sim] changed instruction format so imm12 subs for rs2

[riscv-isa-sim.git] / riscv / insns / mulh.h

diff --git a/riscv/insns/mulh.h b/riscv/insns/mulh.h
index 2d7ca4ceacdf8315a5b9d58e676c54cb7d1380e8..c4fead2db2537d453494ca2b4dc73f24c988c6d8 100644 (file)
--- a/riscv/insns/mulh.h
+++ b/riscv/insns/mulh.h
@@ -1,4 +1,4 @@
 require64;
-int64_t rb = RA;
-int64_t ra = RB;
-RC = (int128_t(rb) * int128_t(ra)) >> 64;
+int64_t rb = RS1;
+int64_t ra = RS2;
+RDR = (int128_t(rb) * int128_t(ra)) >> 64;