Use WRITE_RD/WRITE_FRD macros to write registers

[riscv-isa-sim.git] / riscv / insns / mulh.h

diff --git a/riscv/insns/mulh.h b/riscv/insns/mulh.h
index f771a621d7d0c95777acf8f0ff20150b435d8b45..f63869d7b60aef8605ed86bbe9676460ac345178 100644 (file)
--- a/riscv/insns/mulh.h
+++ b/riscv/insns/mulh.h
@@ -2,7 +2,7 @@ if(xpr64)
 {
   int64_t a = RS1;
   int64_t b = RS2;
-  RD = (int128_t(a) * int128_t(b)) >> 64;
+  WRITE_RD((int128_t(a) * int128_t(b)) >> 64);
 }
 else
-  RD = sext32((sext32(RS1) * sext32(RS2)) >> 32);
+  WRITE_RD(sext32((sext32(RS1) * sext32(RS2)) >> 32));