[xcc] minor performance tweaks

[riscv-isa-sim.git] / riscv / insns / mulh.h

diff --git a/riscv/insns/mulh.h b/riscv/insns/mulh.h
index 90a17be019e35341a1c57ca1a3d361b23917955e..f771a621d7d0c95777acf8f0ff20150b435d8b45 100644 (file)
--- a/riscv/insns/mulh.h
+++ b/riscv/insns/mulh.h
@@ -1,2 +1,8 @@
-RC = sext32((sreg_t(RA) * sreg_t(RB)) >> 32);
-
+if(xpr64)
+{
+  int64_t a = RS1;
+  int64_t b = RS2;
+  RD = (int128_t(a) * int128_t(b)) >> 64;
+}
+else
+  RD = sext32((sext32(RS1) * sext32(RS2)) >> 32);