Use WRITE_RD/WRITE_FRD macros to write registers

[riscv-isa-sim.git] / riscv / insns / mulhu.h

diff --git a/riscv/insns/mulhu.h b/riscv/insns/mulhu.h
index 63344263fe3588a5195eb09fdb5ea075f431d9b1..2d6f48c7e6db30d1a4361afc724f37c0f0b5ba77 100644 (file)
--- a/riscv/insns/mulhu.h
+++ b/riscv/insns/mulhu.h
@@ -1,4 +1,4 @@
 if(xpr64)
-  RD = (uint128_t(RS1) * uint128_t(RS2)) >> 64;
+  WRITE_RD((uint128_t(RS1) * uint128_t(RS2)) >> 64);
 else
-  RD = sext32(((uint64_t)(uint32_t)RS1 * (uint64_t)(uint32_t)RS2) >> 32);
+  WRITE_RD(sext32(((uint64_t)(uint32_t)RS1 * (uint64_t)(uint32_t)RS2) >> 32));