[xcc, sim] changed instruction format so imm12 subs for rs2

[riscv-isa-sim.git] / riscv / insns / mulhuw.h

diff --git a/riscv/insns/mulhuw.h b/riscv/insns/mulhuw.h
index 9f3de3ff630351c141e45e278c2a413af2f7f297..c2a082d8adf33f5378d9c6569039a9733192dba9 100644 (file)
--- a/riscv/insns/mulhuw.h
+++ b/riscv/insns/mulhuw.h
@@ -1,2 +1,2 @@
-RC = sext32((RA * RB) >> 32);
+RDR = sext32((RS1 * RS2) >> 32);