[xcc, sim] changed instruction format so imm12 subs for rs2

[riscv-isa-sim.git] / riscv / insns / mulhw.h

diff --git a/riscv/insns/mulhw.h b/riscv/insns/mulhw.h
index 90a17be019e35341a1c57ca1a3d361b23917955e..7becbfeea07ec3c927250eceed6f3e6b0c9ca7d9 100644 (file)
--- a/riscv/insns/mulhw.h
+++ b/riscv/insns/mulhw.h
@@ -1,2 +1,2 @@
-RC = sext32((sreg_t(RA) * sreg_t(RB)) >> 32);
+RDR = sext32((sreg_t(RS1) * sreg_t(RS2)) >> 32);