[xcc] minor performance tweaks

[riscv-isa-sim.git] / riscv / insns / mulw.h

diff --git a/riscv/insns/mulw.h b/riscv/insns/mulw.h
index d999172c37efcdc8321e6053161ac5918f6ee3e0..7b0a934b68e20ee022e7c871e88dfb8210a413a4 100644 (file)
--- a/riscv/insns/mulw.h
+++ b/riscv/insns/mulw.h
@@ -1,2 +1,2 @@
-RC = sext32(RA * RB);
-
+require_xpr64;
+RD = sext32(RS1 * RS2);