[xcc, sim] changed instruction format so imm12 subs for rs2

[riscv-isa-sim.git] / riscv / insns / mulw.h

diff --git a/riscv/insns/mulw.h b/riscv/insns/mulw.h
index d999172c37efcdc8321e6053161ac5918f6ee3e0..c483fb6f87bcc8bbf868dfcaaa0c46d8a58beb72 100644 (file)
--- a/riscv/insns/mulw.h
+++ b/riscv/insns/mulw.h
@@ -1,2 +1,2 @@
-RC = sext32(RA * RB);
+RDR = sext32(RS1 * RS2);